1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to an internal clock signal generating circuit for a synchronous memory device.
2. Description of the Related Art
Known memory devices, in particular, DRAM, include asynchronous DRAM and synchronous DRAM (hereinafter, referred to as SDRAM). The internal signals in the SDRAM are synchronized with external clock signals input from an external CPU. Thus the SDRAM generates internal clock signals having a predetermined pulse width synchronized with respect to the external clock signals.
FIG. 1 is a circuit diagram of a conventional internal clock signal generator of an SDRAM. Referring to the drawing, the conventional internal clock signal generator includes: an inverter I1 for inverting an external clock signal (Clock) input thereto by an external CPU; a delay portion 1 for delaying the output from the inverter I1; and a NAND gate ND1 for performing a NAND operation with respect to the outputs of the inverter I1 and the delay portion 1 and outputting an internal clock signal (Pclock). The delay portion 1 includes a series of inverters I2 to I7. The phase of the internal clock signal (Pclock) is determined by the state of the external clock signal (Clock). Here, a detailed description of the operation of the conventional internal clock signal generator is omitted.
FIGS. 2 and 3 are timing diagrams for the conventional internal clock signal generator shown in FIG. 1. FIG. 2 shows a case in which the cycle of the external clock signal (Clock) is relatively long. FIG. 3 shows a case in which the cycle of the external clock signal (Clock) is relatively short--in both cases relative to the Pclock logic-low pulse width FIG. 4 shows an example of a circuit using an internal clock signal in an SDRAM. A problem with the conventional internal clock signal generator of FIG. 1 will be described with reference to FIG. 4.
Referring to FIG. 4, when an internal clock signal (Pclock) is toggled to a logic "high", an input signal (Input), input through a transmission gate TM1 is stored in a latch 3. When the internal clock signal (Pclock) is toggled to a logic "low", the signal stored in the latch 3 is output through a transmission gate TM2 and stored in a latch 5, and then output as an output signal (Output). In order to accurately transmit the input signal (Input) as the output signal (Output), the pulse width of the internal clock signal (Pclock) must be longer than the input and output response times of the transistors used in FIG. 4. However, in the conventional internal clock signal generator, as shown in the timing diagram of FIG. 3, when the cycle of the external clock signal (Clock) is short (i.e. high frequency), the Pclock "low" pulse width is reduced. If the cycle of the external clock signal (clock) is extremely shortened, the "low" pulse width of the internal clock signal (Pclock) can disappear entirely. Thus, when the "low" pulse width of the internal clock signal (Pclock) is shorter than the input and output response times of the transistors used in FIG. 4, the input signal (Input) is not accurately transmitted as the output signal (Output), and a malfunction occurs.